1. Field of the Invention
The present invention relates generally to MOSFET devices, and more specifically, to trench-type MOSFET devices with ultra-shallow source regions and low temperature process flows.
2. Description of Related Art
Trench type power semiconductor devices such as power MOSFETs are well known. Referring to FIG. 1, there is illustrated an example typical power MOSFET 10, which includes a plurality of trenches 12 formed in semiconductor body 14. Semiconductor body 14 is usually a silicon die that includes an epitaxially grown silicon layer (epitaxial silicon layer) 16 of one conductivity (e.g. N-type) formed over a silicon substrate 18 of the same conductivity, but of higher concentration of impurities. A channel region 20 is formed in epitaxial silicon layer 16 and extends from the top surface of the semiconductor body to a first depth. Channel region 20 has a conductivity opposite to that of epitaxial layer 16 (e.g. P-type). Formed within channel region 20 are source regions 22, which have the same conductivity (e.g. N-type) as epitaxial silicon layer 16.
As is well known, trenches 12 extend through channel region 20 to epitaxial silicon layer 16. Lining the sidewalls and bottom surfaces of these trenches are gate insulation layer 24, which may be formed with silicon dioxide, for example. Within each trench 12 is gate electrode 26, which is typically composed of conductive polysilicon.
Example MOSFET 10 further includes a source electrode 28, which is electrically connected to source regions 22, and a high conductivity contact region 30, which is also formed in channel region 20. High conductivity contact region 30 is highly doped with dopants of the same conductivity as channel region 20 (e.g. P-type) in order to reduce the contact resistance between source contact 28 and channel region 20. Example MOSFET 10 further includes a drain electrode 32, which is in electrical contact with silicon substrate 18.
As is know, it is generally desirable for source regions 22 to extend deep enough into the semiconductor body so that they vertically overlap gate electrodes 26 (as illustrated by region 30 in FIG. 1). In this fashion, the gate electrodes fully overlap channel region 20 and allow for the formation of an accumulation region through the channel region so that current will flow between source electrode 28 and drain electrode 32. As is also known, source regions 22 are often formed, for example, by implanting dopants into the semiconductor body and then applying sufficient temperature for a sufficient time to diffuse the dopants to the desired depth. As illustrated in FIG. 1, gate electrodes 26 are often recessed within trenches 12 below the top surface of the semiconductor body, as illustrated by distance 32. As such, when forming source regions 22, sufficient temperatures and process times are needed to vertically diffuse the dopants at least through distances 32 and 30 so that there is overlap with the gate electrodes. However, for several reasons it is generally desirable to reduce the vertical depth of the source regions and as such, to minimize the amount of vertical diffusion needed to form these regions.
For example, larger vertical diffusions require higher diffusion temperatures and/or process times. However, increased temperatures and process times will generally affect fabrication costs and/or affect device performance. For example, high temperature process steps can adversely affect previously performed low temperature steps. As such, the high temperature steps must be performed before the low temperature steps, if possible. Alternatively, for example, the high temperature steps must be performed at reduced temperatures but at the cost of increased process times.
Another problem with larger vertical diffusions for source regions is that dopants do not only move vertically, but also laterally during diffusion. Hence, creating source regions with larger vertical depths also results in source regions with greater lateral length across the surface of the semiconductor device. However, this lateral diffusion is generally undesirable because it means the distance between trenches has to be increased. Increasing the distance between adjacent trenches, however, increases cell size. As is known, it is generally desirable to reduce the distance between trenches so that the number of trenches for a given die area can be increased, thereby reducing cell size and increasing the current the device can handle.
A further problem with larger vertical diffusions for source regions is that as the vertical depth of the source regions increases, the vertical depth of channel region 20 into epitaxial silicon layer 16 must also increase. However, an increased channel region depth also means that the length/depth of trenches 12 needs to increase so that the trenches extend into epitaxial silicon layer 16. In turn, increased trench depth means that the gate electrode length must also increase. However, as is known, it is generally desirable to reduce the gate electrode length in order to reduce gate charge (Qg) and thereby improve the efficiency of the device.